1. Field of the Invention
The present invention relates to a wafer level chip scale package of an image sensor and a manufacturing method thereof. In the wafer level chip scale package of the image sensor, since expansion pads are provided instead of solder balls, a complicated process of forming solder balls can be omitted, thereby improving production capability. Since a glass is attached in a wafer level, defects caused by foreign particles can be minimized. Furthermore, miniaturization and slimness of the package can be realized.
2. Description of the Related Art
One of main trends in today's semiconductor industries is to miniaturize semiconductor devices as much as possible. The miniaturization is absolutely required in semiconductor chip package industries. Packaging is a technology that mounts an integrated circuit (IC) chip, where microcircuits are designed, onto an electronic device and seals it using a plastic resin or ceramic.
A typical package has a size much greater than an IC chip embedded therein. Therefore, package technicians have been interested in reducing the package size to a chip size level.
One of recently developed packages is a chip scale package (also called a chip size package). In particular, compared with a typical package method of assembling packages based on an individual chip, a wafer level chip scale package has features in that packages are assembled and manufactured in a wafer level.
The advance of semiconductor IC chips leads to the advance of package technologies, realizing high density, high speed, miniaturization, and thinning. More specifically, package devices are changing from a “pin insert type” or “through hole mount type” to a “surface mount type” in a structural aspect. In this way, a packaging density with respect to a circuit board is increased. Recently, studies have been actively conducted on chip size packages (CSPs) that can reduce the package size to a chip level while maintaining a characteristic of a bare chip at a package state.
In the case of a wafer level chip scale package (WLCSP) among chip size packages, chip pads are rerouted or redistributed on a chip surface, and solder balls are then formed. In the wafer level chip scale package, chips or dies are directly mounted onto a circuit board in a so-called flip chip scheme, and solder balls formed on the circuit where chips are rerouted are attached to conductive pads of the circuit board. Since solder balls are also formed on the conductive pads, they are attached to the solder balls of the package.
Recently, a variety of CSP technologies have been introduced which can make the chip size so small that there is almost no difference between the sizes of the semiconductor chip and the package. With the trends of miniaturization, high speed, and high integration, these technologies have spread faster than expected.
A wafer level package technology is considered as a next generation CSP technology. In the wafer level package technology, all assembling processes are finished in a wafer level where chips are not cut out. While a typical assembling process is performed after cutting the wafer into individual chips, the wafer level package technology is to perform a series of processes, e.g., a die bonding, a wire bonding, a molding, etc. in a wafer level where chips are attached to one another and then make final products by cutting the wafer into individual chips.
This technology can further reduce a total package cost than any other CSP technology.
In such a wafer level chip scale package, solder balls are formed on an active surface of a semiconductor chip. Due to this structure, there is a great structural difficulty in stacking the wafer level chip scale package or applying it to manufacture a sensor package such as a charge coupled device (CCD).
Korean Patent Laid-Open Publication No. 2002-74158 discloses a packaged IC device in which a package of an image sensor is manufactured using the wafer level chip scale package technology. The structure of the packaged IC device is illustrated in FIG. 1.
FIG. 1 is a cross-sectional view of an IC device having a microlens array 100 formed on a crystalline substrate.
Referring to FIG. 1, a packaging layer 106 is formed of glass under a crystalline substrate 102 where a microlens array 100 is formed on its surface. The packaging layer 106 is sealed by an epoxy 104. Electrical contacts 108 are formed along edges of the packaging layer 106. The electrical contacts 108 are connected to bumps 110, which are formed on the bottom surface of the packaging layer 106. In addition, the electrical contacts 108 are connected to conductive pads 112, which are formed on the top surface of the substrate 102.
A packaging layer 114, typically formed of glass, and associated spacer elements 116 are sealed over the substrate 102 by an adhesive such as an epoxy 118, thereby defining a cavity 120 between the microlens array 100 and the packaging layer 114.
The electrical contacts 108 are formed on inclined surfaces of the epoxy 104 and the packaging layer 106 by a plating process or the like.
In the conventional IC device, the electrical contacts 108 are formed so as to electrically connect the conductive pads 112 and the bumps 110. However, the reliability of connection is low because the conductive pads 112 and the electrical contacts 108 are connected in a face-to-face manner, and the structure and process become complicated because the IC device is manufactured by a stacking process.
International Patent Publication No. WO 99/040624 and Korean Patent Laid-Open Publication Nos. 2000-2962 and 2002-49940 disclose semiconductor devices having high-reliability ball grid array (BGA) using the wafer level chip scale package technology. In these semiconductor devices, solder bumps with solder balls mounted thereon are formed in order for electrical connection to pad electrodes. The formation of the solder balls requires a lot of forming processes and is complicated. Hence, the productivity of the semiconductor devices is low because of the increase in the number of the forming processes.
Furthermore, in the conventional chip scale package with the solder balls mounted thereon, a plurality of solder balls protrude downwardly. Therefore, the side or bottom surface of the package cannot be directly connected to a separate printed circuit board (PCB) or ceramic substrate during a hot bar process performed in manufacturing a socket type camera module. Consequently, separate contacts must be further provided for electrical connection of the package.